Backup domain control register (RCC_BDCR)

Address offset: 0x20

Reset value: 0x0000 0000, reset by Backup domain Reset.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register

(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected

and the DBP bit in the Power control register (PWR_CR) has to be set before

these can be modified. Refer to Section 5 on page 58 for further information. These bits are

only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any

internal or external Reset will not have any effect on these bits.