APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait states, except if the access occurs while an access to a peripheral in the APB2

domain is on going. In this case, wait states are inserted until the access to APB2 peripheral

is finished.

Note: When the peripheral clock is not active, the peripheral register values may not be readable

by software and the returned value is always 0x0.