APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait state, except if the access occurs while an access to a peripheral on APB1 domain

is on going. In this case, wait states are inserted until this access to APB1 peripheral is

finished.

Note: When the peripheral clock is not active, the peripheral register values may not be readable

by software and the returned value is always 0x0.